The present invention relates to an MOS semiconductor device including MOS transistors whose effective channel length is 1 .mu.m or less, for example.
The development of MOS semiconductor devices has progressed remarkably. In the latter half of 1960s, the number of MOS transistors that could be integrated into one semiconductor chip was several hundred at most, with the effective channel length being approximately 10 .mu.m. Since, then, the microfabrication technology and high density integration technology have significantly advanced so that it is possible to form hundreds of thousand of MS transistors having a channel length of 1.5 .mu.m on a single chip. Further, semiconductor devices which are operable at a high speed with low power consumption can be realized by forming MOS transistors having a channel length of 1 .mu.m or less and at a high density.
The conventional MOS transistor circuit employs an external power source for driving the internal circuit. The voltage of the power source must be reduced the shorter the effective channel length becomes of MOS transistors contained in the internal circuit to be driven. To drive an MOS transistor with an effective channel length of 1.5 .mu.m, for example, a single power source is used and its output voltage is approximately 5 V. To drive a MOS transistor with an effective channel of 1.0 .mu.m, a lower power source voltage than 5 V should be used. If a voltage of 5 V is applied to a MOS transistor having a channel length of 1.0 .mu.m, an intense electric field is developed in the channel region of the MOS transistor. High energy carriers are trapped in the insulating oxide film, causing possible deterioration in the operating characteristics of the MOS transistor.
In the conventional MOS semiconductor device have been unsatisfactory for preventing, for example, a leak current from flowing while a voltage lower than the threshold voltage is being applied, a voltage applied to the source or drain diffusion layer from undershooting, and the formation of junction capacitance associated with the diffusion layers. In the case of a semiconductor device which includes two n-channel MOS transistors TN1 and TN2, as shown in FIG. 1, a self-substrate bias circuit 1 has been provided for setting the back gates of the transistors TN1 and TN2 at a lower potential than the ground potential, thereby inversely biasing th junction between the source or drain diffusion layer and the substrate. This approach, however, requires the generation of a negative bias voltage from the self-substrate bias circuit 1 even when the integrated circuit is in a standby mode, increasing power consumption of the device as a result of the self-substrate bias circuit 1.
In order to apply a negative bias voltage to the back gates of the n-channel MOS transistors, CMOS devices have been considered. When a CMOS device is used a self-substrate bias circuit of high impedance is provided between the emitter and base of an npn transistor constituted by the source or drain diffusion region of the n-channel MOS transistor, the p-well, and an n-type substrate in the CMOS device. This arrangement makes the latch-up phenomenon peculiar to CMOS devices a serious problem.